1. Field of the Invention
The present invention relates to the field of semiconductor memory devices and, more particularly to a dynamic random access memory (DRAM) cell with a non-volatile memory component and a static random access memory (SRAM) cell with a non-volatile memory component.
2. Description of the Related Art
An essential semiconductor device is semiconductor memory, such as a random access memory (RAM) device. A RAM device allows the user to execute both read and write operations on its memory cells. Typical examples of RAM devices include dynamic random access memory (DRAM) and static random access memory (SRAM).
DRAM is a specific category of RAM containing an array of individual memory cells, where each cell includes a capacitor for holding a charge and a transistor for accessing the charge held in the capacitor. The transistor is often referred to as the access transistor or the transfer device of the DRAM cell.
FIG. 1 illustrates a portion of a DRAM memory circuit containing two neighboring DRAM cells 10. Each cell 10 contains a storage capacitor 14 and an access field effect transistor or transfer device 12. For each cell, one side of the storage capacitor 14 is connected to a reference voltage (illustrated as a ground potential for convenience purposes). The other side of the storage capacitor 14 is connected to the drain of the transfer device 12. The gate of the transfer device 12 is connected to a signal known in the art as a word line 18. The source of the transfer device 12 is connected to a signal known in the art as a bit line 16 (also known in the art as a digit line). With the memory cell 10 components connected in this manner, it is apparent that the word line 18 controls access to the storage capacitor 14 by allowing or preventing the signal (representing a logic "0" or a logic "1") carried on the bit line 16 to be written to or read from the storage capacitor 14. Thus, each cell 10 contains one bit of data (i.e., a logic "0" or logic "1").
Referring to FIG. 2, an exemplary DRAM circuit 40 is illustrated. The DRAM 40 contains a memory array 42, row and column decoders 44, 48 and a sense amplifier circuit 46. The memory array 42 consists of a plurality of memory cells (constructed as illustrated in FIG. 1) whose word lines and bit lines are commonly arranged into rows and columns, respectively. The bit lines of the memory array 42 are connected to the sense amplifier circuit 46, while its word lines are connected to the row decoder 44. Address and control signals are input into the DRAM 40 and connected to the column decoder 48, sense amplifier circuit 46 and row decoder 44 and are used to gain read and write access, among other things, to the memory array 42.
The column decoder 48 is connected to the sense amplifier circuit 46 via control and column select signals. The sense amplifier circuit 46 receives input data destined for the memory array 42 and outputs data read from the memory array 42 over input/output (I/O) data lines. Data is read from the cells of the memory array 42 by activating a word line (via the row decoder 44), which couples all of the memory cells corresponding to that word line to respective bit lines, which define the columns of the array. One or more bit lines are also activated. When a particular word line and bit lines are activated, the sense amplifier circuit 46 connected to a bit line column detects and amplifies the data bit transferred from the storage capacitor of the memory cell to its bit line by measuring the potential difference between the activated bit line and a reference line which may be an inactive bit line. The operation of DRAM sense amplifiers is described, for example, in U.S. Pat. Nos. 5,627,785; 5,280,205; and 5,042,011, all assigned to Micron Technology Inc., and incorporated by reference herein.
DRAM devices are the most cost effective high speed memory used with computers and computer systems. They last (nearly) indefinitely and are available in very high density. They are, however, limited in the longevity of their memory. DRAM devices require constant refreshing and lose all knowledge of their state (i.e., contents) once power to the device is removed. It is desirable to have a memory device, such as a DRAM memory device, with all of the positive features of DRAM devices, e.g., cost, size, speed, availability, etc., that retains its memory state when power is removed from the device. That is, it is desirable to have DRAM cells with a nonvolatile memory component built within the cell.
A DRAM cell with a nonvolatile component would be very beneficial in numerous computer systems and computer applications. One application would be the saving and/or restoring of the state of a central processing unit (CPU) that is executing software instructions in a protected mode of operation, an example of which is disclosed in U.S. Pat. No. 5,497,494 to Combs et al., which is hereby incorporated by reference in its entirety. This application typically involves the use of memory separate from the main memory of the computer, typically referred to as shadow RAM, from which a BIOS program is executed and the CPU state is to be stored to and retrieved from. Having a DRAM device constructed with DRAM cells having a nonvolatile component would eliminate the need to have the separate shadow RAM.
This holds true for other computer systems that utilize shadow memory, such as, for example, the fault tolerant system disclosed in U.S. Pat. No. 5,619,642 to Nielson et al., which is hereby incorporated by reference in its entirety. In a fault tolerant system, a main memory contains data and error detection codes associated with each piece of data. A separate shadow memory is used to store data corresponding to the data stored in the main memory. If the system determines that accessed data from the main memory is erroneous, the corresponding data from the shadow memory is used and thus, faults in the main memory do not adversely effect the system (i.e., the system is fault tolerant). Again, memory separate from the main memory is required, which adds cost and adds to the size and complexity of the system. Having a DRAM device constructed with DRAM cells having a nonvolatile component would eliminate the need to have the separate shadow memory.
There has been attempts to include shadow memory on DRAM and SRAM devices, such as the memory disclosed in U.S. Pat. No. 5,399,516 to Bergendahl et al. and U.S. Pat. No. 5,880,991 to Hsu et al. These devices, however, place individual DRAM and/or SRAM cells on the same substrate as separate nonvolatile memory cells. They do not use a single DRAM (or SRAM) cell having its own integral nonvolatile component. Instead, separate cells are used, which adds cost, size and complexity to the memory. Having a DRAM device constructed with DRAM cells having a nonvolatile component would eliminate the need to have the separate DRAM and nonvolatile cells. A DRAM with a nonvolatile component would have many other uses in addition to those described by way of example herein.
SRAM devices are another form of RAM device. SRAM devices differ from DRAM devices in that they do not require constant refreshing. A standard SRAM cell 200 is shown in FIG. 3a. Cell 200 consists of four transistors 206, 208, 210, 212, and two control transistors 202 and 204. Data is stored with either a high potential at node A and a low potential at node B, or a low potential at node A and a high potential at node B. This means that two stable states are available which are defined as a logic "1" or a logic "0".
Cell 200 is embedded in an array of similar cells as shown in FIG. 4. A typical SRAM consists of a matrix of storage bits with bit capacity 2.sup.N .times.2.sup.M bits arranged in an array 275 with 2.sup.M columns (bit lines) and 2.sup.N rows (word lines).
To read data stored in the array 275, a row address is input and decoded by row decoder 280 to select one of the rows or word lines. All of the cells along this word line are activated. Column decoder 282 then addresses one bit out of the 2.sup.M bits that have been activated and routes the data that is stored in that bit to a sense amplifier (not shown) and then out of the array 275. Data in and Data out are controlled by the Read/Write Control circuit 284.
Referring again to FIG. 3a, the logic state of SRAM cell 200, i.e., either a "1" or "0", is read by sensing the cell current on bit line pair comprised of bit lines 216 and 217 and/or the differential voltage developed thereon. When word line 218 is selected, cell 200 is activated by turning on control transistors 202 and 204. If the activated SRAM cell 200 is in logic state "1" node A is high and node B is low. Transistor 208 will be off, transistor 212 will be on, transistor 206 will be on, and transistor 210 will be off. Since transistors 212 and 204 are on, bit line 217 will carry cell current, while bit line 216 will not carry any cell current since transistor 208 is off.
The logic state "0" would be the opposite with node A low and node B high. Transistor 208 will be on, transistor 212 will be off, transistor 206 will be off, and transistor 210 will be on. Bit line 216 will carry cell current, while bit line 217 will not carry cell current.
FIG. 3b illustrates an alternative SRAM cell 250. In this cell 250, transistors 206 and 210 are replaced by two resistors 252, 254. The operation of the cell 250, however, is essentially the same as the operation of the cell 200 (FIG. 3a). The SRAM cell 250 can also be used in and accessed from the SRAM device illustrated in FIG. 4.
Although SRAM devices have their advantages, e.g., they do not require constant refreshing, they are not without their shortcomings. For example, similar to DRAM devices, SRAM devices also lose all knowledge of their state once power to the device is removed. A SRAM utilizing SRAM cells having a nonvolatile component would also be suitable for use in a computer system for startup/restart from protected mode and other shadow memory applications. Accordingly, there is a desire and need for a SRAM memory device that retains its memory state when power is removed from the device. That is, it is desirable to have SRAM cells with a nonvolatile memory component built within the cell.